Silicon (Si) based photonics have the potential to offer large savings in photonic integrated circuits by leveraging the economies of scale using cost-efficient technology with equipment that is readily available in complementary metal-oxide semiconductor (CMOS) foundries. In addition, the high refractive index contrast achievable with silicon confines light more efficiently and allows tighter bends thereby making photonic integrated circuits much smaller. Most optical functions (except a light source) can be fabricated using silicon. In particular, the performance of integrated germanium detectors and silicon modulators is very encouraging. Improved integration and complex PICs are potentially possible.
Today's problem with silicon based photonics is that the performance of passive functions in silicon, e.g. an arrayed waveguide grating (AWG) or splitter, is insufficient. This limits the usefulness of the technology for complex PICs integrating active and passive functions.
A solution offering a high quality silicon nitride (SiN) platform is described in the article entitled “Planar Waveguides with less than 0.1 dB/m propagation loss fabricated with wafer bonding” from the authors J. F. Bauters et al., published in Optics Express, Vol. 19, No. 24, on 21 Nov. 2011.
Application of platforms offering high quality silicon nitride (SiN) waveguides like the one reported by Bauters et al., is limited since it is hard to envisage how active photonic devices like detectors and modulators can be fabricated in a silicon nitride-only platform.
Alternatively, several papers demonstrate PICs using silicon-only waveguides. As already indicated above, a silicon-only platform however can only offer passive devices like an AWG or splitter with limited performance.
Thirdly, various solutions combining silicon waveguides for active devices with silicon nitride waveguides for passive structures have been proposed in literature. The following paragraphs briefly discuss some of them.
In the article “Eight-Channel SiO2/Si3N4/Si/Ge CWDM Receiver” from the authors C. R. Doerr et al., published on 1 Sep. 2011 in IEEE Photonics Technology Letters, Vol. 23, No. 17, pages 1201-1203, a silicon nitride layer is deposited though plasma-enhanced chemical vapor deposition (PECVD) after the active silicon photonics devices have been fabricated.
In the platform known from Doerr et al., the choice to fabricate the silicon nitride layer after the silicon photonic active devices have been fabricated severely limits the available thermal budget. This is why the deposition technique chosen for the silicon nitride layer is PECVD. Unfortunately, PECVD based silicon nitride has several problems. Firstly the hydrogen content is relatively high which increases optical losses especially around 1530 nanometer which is in the telecom wavelength range. Also the thickness and refractive index uniformity is far worse than for example with low-pressure chemical vapor deposition (LPCVD) based silicon nitride. LPCVD however typically requires temperatures above 780 degrees Celsius (° C.) which would damage the silicon photonic active devices.
The article “Monolithic Integration of Silicon-, Germanium-, and Silica-Based Optical Devices for Telecommunications Applications” from the authors T. Tsuchizawa et al., published in IEEE Journal of Selected Topics in Quantum Electronics, Vol. 17, No. 3, May/June 2011, describes deposition at low temperature of a silicon rich oxide layer after the silicon photonic active devices have been fabricated.
In the process and platform known from T. Tsuchizawa et al., a low temperature electron-cyclotron resonance chemical vapor deposition (ECR-CVD) process is used. The reported propagation loss stays above 1.5 decibels (dB)/centimeter (cm), and uniformity of the layer is not disclosed.
In the article “CMOS-Compatible Scalable Photonic Switch Architecture Using 3D-Integrated Deposited Silicon Materials for High-Performance Data Center Networks” published in Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 19-23 Sep. 2010, the authors A. Biberman et al. calculate the performance of a switch using a high quality silicon nitride layer and an amorphous silicon layer.
Although Biberman et al. propose to use a high quality low loss silicon nitride layer, the silicon layer proposed is not mono-crystalline but deposited as amorphous or polycrystalline silicon by LPCVD techniques. It is therefore not possible to use this layer to fabricate integrated germanium detectors—a key component for PICs—in this layer.
International patent application publication 00/65393 from Centre National de la Recherche Scientifique, entitled “Photonic Integrated Circuit Comprising a Resonant Optical Component and Methods for Making Same” illustrates in FIG. 6 and the corresponding paragraphs an embodiment wherein a first wafer receives an SiO2 underclad layer (8) and Si waveguide layer (16). Through wafer bonding, a Si3N4 layer (20) is transferred. The layers 16 and 20 are vertically coupled through evanescent coupling. Although it also seems to be an objective of International patent application publication 00/65393 to separate the manufacturing of active and passive components, the passive structures are manufactured in the silicon waveguide layer (16) whereas active structures (laser) are manufactured in the silicon nitride layer. As already indicated here above, the performance of such silicon based passive structures is insufficient.
United States Patent Application Publication 2009/0016399 entitled “Hybrid Silicon Evanescent Photodetectors” discloses in FIG. 8 and the corresponding paragraphs [0055]-[0059] a photodetector that is obtained by bonding a second wafer with a Group III-V structure onto a first wafer with silicon-on-insulator (SOI) structure. The SOI wafer contains a passive waveguide.
The teaching of United States Patent Application Publication 2009/0016399 is not applicable for manufacturing high quality photonic devices integrating active and passive structures for several reasons. Firstly, United States Patent Application Publication 2009/0016399 suggests to manufacture passive structures in the silicon waveguide layer on the first layer. The performance of such silicon based passive structures is insufficient for photonic circuits integrating active and passive photonic functions. Further, the III-V wafers are only available in much smaller wafer sizes than silicon. Bonding III-V wafers onto silicon wafers consequently results in high waste. Once bonded, the III-V wafer and SOI wafer cannot be processed anymore through processes that are compatible with CMOS wafer fabrication. The technology required to perform the processing after bonding in United States Patent Application Publication 2009/0016399 consequently is not expected to be readily available in CMOS foundries as a result of which the processing becomes more complex and expensive.
It is an objective of the present invention to disclose a process for manufacturing a photonic circuit integrating active and passive photonic functions that overcomes the above mentioned drawbacks of existing solutions. More particularly, it is an objective to disclose such a process that enables integrating high performing passive optical structures with active optical devices in a platform that can be manufactured using technology available in CMOS foundries without a risk for damaging the active photonic devices.